a) Field of the Invention
This invention relates to a receiving apparatus and a method therefor for synchronising a digital data clock in a receiver with a digital data clock in a transmitter.
b) Description of the Prior Art
It is known in digital electronic systems to send digital data from one device (a transmitter) to another device (the receiver). In many such systems a single cable is used as the transmission media between the two devices in which the data is converted into individual binary digits (bits) of information which are serially transmitted along the cable.
Some form of encoding is required to represent each of the bits of data to be transmitted and one common form of encoding is the so-called "no return to zero" (NRZ) of which an exemplary waveform is shown in FIG. 1(a). Referring to FIG. 1(a) each data bit has one of two values which are represented by high and low voltage levels on the cable, the low voltage levels being represented by data level "0" and the high voltage levels being represented by data level "1". To correctly decode the data it is necessary for the receiver to know at what point to sample the incoming waveform. In instances where the transmitter and receiver share a common clock then synchronisation is relatively straightforward but it is not usually the case that the transmitter and receiver share a common clock and so it then becomes necessary for the receiver to generate its own clock with which it samples the incoming data. Although this may not represent any problems for short data streams, there will invariably be problems with frequency variations between the transmitter and receiver clocks, particularly if the data stream contains long periods of one particular logic level which give the receiver no information about the clock of the transmitter.
It is, therefore, desirable to transmit the data and the clock used to generate it. One known encoding method used to enable the clock and data to be sent down a single cable is so-called "Manchester" encoding, a typical waveform of which is shown in FIG. 1(b) corresponding to the NRZ data waveform shown in FIG. 1(a). It will be noted that from FIG. 1(b) that each data bit is split into two halves, the first half of each bit period being set equal to the inverse of the data bit to be sent and the second half being set equal to the data bit to be sent. The relevant and important feature of the waveform of FIG. 1(b) is that there is a transition in the middle of every bit period regardless of the data which is being sent.
At the start of data transmission a preamble of alternating 0's and 1's is transmitted and such a preamble waveform for the NRZ data is shown in FIG. 2(a) and for the Manchester encoded data is shown in FIG. 2(b). The Manchester encoded data preamble waveform, as shown in FIG. 2(b), only has transitions in the middle of every bit period and not at the end of the bit periods, and it is a square wave at exactly half the frequency of the transmitted NRZ data rate shown in FIG. 2(a). The receiver is, thus, able to use the preamble to synchronise its own clock and the ensuing transition in the middle of every bit period is used to maintain the synchronisation.
It is known to use a phase-locked loop (PLL) to perform the receiver clock synchronisation and in a conventional receiver the Manchester encoded data is decoded by using the receiver clock to sample the incoming data. Thus, to correctly decode the data the receiver clock must match the transmitter clock to within a quarter of a bit period or the data may be sampled on the wrong side of a transition in the data. The receiver must also be able to cope with jitter in the incoming data stream, that is in which the individual edges of the waveform may be shifted by a significant amount from their normal position. Thus, to take ETHERNET as an example, the bit period is 100 ns and so the receiver clock must be accurate to .+-.25 ns. It is also possible to have jitter of up to 18 ns--as specified in ISO Standard 8802.3--which means that, as an absolute minimum, the accuracy of the receiver clock must be .+-.7 ns.
Until relatively recently the majority of high-speed phase-locked loops were analogue in nature and these had the advantage of having an infinite resolution but required the use of accurate capacitors and resistors which makes them unsuitable for integration into digital integrated circuits.
A digital phase-locked loop requires no such precision components. However, its resolution is very much limited by its sampling frequency. Therefore, to take the example of ETHERNET, if it was decided that a clock accuracy of .+-.5 ns was required, this would require a 200 MHz sampling rate in a conventional digital phase locked loop. This is above the maximum clock frequency achievable in most current silicon technologies.
It is an object of the present invention to provide a receiving apparatus for synchronising a digital data clock in a receiver with a digital data clock in a transmitter and to provide a method therefor.